A roadmap to emulation of 15 billion-gate ICs

Mentor Graphics is introducing an emulation platform in its roadmap for the next five years.

Mentor Graphics Corp. is breaking with EDA's standard procedure, rolling out an emulation platform that the company says supports a roadmap to 2022, when it will be capable of handling chip designs with 15 billion gates.

"This is not a typical EDA announcement, because we are announcing a platform that basically will carry over for five years," said Jean-Marie Brunet, a senior director of marketing at Mentor, in an interview with EE Times. "We are not going to come back in two years and say, 'Forget what we said in 2017, here's a new platform.' Everything that we are going to do for the next four to five years is around that Veloce StratoM platform."

Emulation is a bit different than the rest of EDA in that it relies on a very costly hardware component. According to Brunet, today's most cutting-edge chip designs-advanced CPUs, GPUs, CPU and GPU combinations, and network processors-feature about 1.5 billion gates. By 2022, Mentor expects that number to increase tenfold to reach 15 billion gates.

The Veloce StratoM is already in use by major chip companies, Brunet said, adding that he could not identify them. The emulator is capable of 2.5 billion-gate capacity when fully loaded and the total capacity increases as the number of emulators are connected together via Mentor's Veloce Strato link, he said.

To read the full article, go to EE Times.