ARM offers support for TSMC 7nm manufacturing

Global SourcesUpdated on 2023/12/01

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The Artisan physical IP platform will be ready for tape-outs in 1H17.

Layout utilization of design before and after using Power Grid Architect or PGA resulting in 10 percent area reduction and an effective utilization rate improvement of 20 percent. Source: ARM via EE Times

ARM Ltd announced the availability for evaluation and licensing of its Artisan physical IP platform for the 7nm 7FF FinFET process from TSMC, as well as a design win at that level with Xilinx Inc.

The IP set does not include support for EUV lithography, which is expected to be deployed later.

"The physical IP platform is available for tape-outs in 1H17. We see some engineering samples in 2017," Ron Moore, vice president of marketing in the physical design group at ARM, told EE Times Europe. However, it is not clear that there is a performance, power or area benefit in selecting the 7FF process over the 10FF process.

The 10FF was a marked scaling over 16FF+ that could produce a 20 percent speed increase at the same power, or more than 40 percent power reduction at the same speed, according to past reports (see TSMC Symposium: 10nm is ready for design starts). But it came at the cost of the increased use of double patterning.

To read the full article, go to EETimes.

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