ARM sizes up Moore's law

Memory wall and cost per transistor are tackled.

It is getting harder and more costly to make chips smaller and faster, but there is still hope for advancing Moore's law, according to a keynote at the annual International Electron Devices Meeting or IEDM in Washington, DC recently. In a broad and balanced talk, a senior researcher at ARM detailed the variety of techniques and challenges ahead.

"The semiconductor industry will need to push equivalent Moore's law scaling through a broadening set of fronts … in an 'all-of-the-above' effort [that] will include more technology complexity, investment in technology-design optimizations, and ultimately technology-system optimizations," Greg Yeric of ARM Research in Austin wrote in an IEDM paper.

To combat "an increasing set of design limitations, including power limits, parasitics, variability and, of course, cost," engineers will need to employ a host of remedies that could "fragment and possibly dilute economies of scale," Yeric wrote. As a result, "it is possible to foresee significant sacrifices in density for the sake of schedule … [and] understanding the cost versus benefit of potential changes will become more complicated."

The problem "is perhaps most acute in memory [where] DRAM scaling is waning just as many applications are demanding exploding amounts and levels of memory."

Yeric suggested the move to chip stacks, which layer memory and logic devices, looks more promising than the current field of alternative memory architectures.

To read the full article, go to EETimes.

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