Design rule checking for SerDes PCB layouts

Global SourcesUpdated on 2023/12/01

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In addition to manual inspection to be sure the SerDes bus traces on a routed board are error-free, use of an automated design rule checker makes such tasks easier.

Impedance discontinuities such as neckdowns in chip breakout regions and tuning loops can occur any place where the target trace width and/or spacing is changed.
Source: EETimes

Despite running at much faster speeds than parallel interfaces, SerDes buses tend to be much easier to implement, as there is a specific set of problems to overcome. As long as the high-level architecture of the SerDes interface is sound, a successful implementation of a SerDes bus boils down to "implementation details." Such details must usually be verified by manual inspection of the routed board, but an automated inspection methodology, facilitated through the use of design rule checking or DRC, can make the task of reviewing SerDes buses much easier. Here are examples where DRC can be useful:

  • Targeting differential impedance
  • Watching out for via discontinuities
  • Paying attention to reference planes
  • Differential pair routing considerations
  • To read the full article and see the specifics of where DRC can be useful, please go to EETimes.

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