Sony Corp. revealed that the company's next-generation Global Navigation Satellite System (GNSS) chip will use 28-nm Fully Depleted Silicon On Insulator (FDSOI) process.

The test chip based on the FDSOI process marks a dramatic reduction in power consumption. A Sony engineer, who spoke at the SOI Industry Consortium in Tokyo, told the audience that Sony was able to cut power consumption in its GNSS chip from 10mW to 1mW.

The Japanese company used STMicroelectronics' 28nm FDSOI design kit, and manufactured its FDSOI samples.

While stopping short of announcing a launch date for the chip, the Japanese company shared at the forum its own FDSOI "design experience," giving it a thumb's up. The speaker Kenichi Nakano from Sony gave a presentation entitled "Low Power SoC design with RF circuit by the FDSOI 28nm."

An STMicroelectronics representative told EE Times, "FDSOI is no longer just an ST story anymore." If the SOI Forum is any measure, the FDSOI ecosystem is coming together. Other presenters included Samsung, Verisilicon, Open Silicon, Synopsys and Cadence. They reported their own results and IP with FDSOI.

Sony's new chip for wearables

Sony's current-generation GPS chip, designated CXD5600GF, was announced in 2013, and was touted then as the world's smallest measuring 2.9mmx3mmx0.6mm, as well as the lowest in power consumption (at 10mW when continuously receiving signals).

In an interview with the Nikkei Technology Online, Sony's Nakano said, "While the CXD5600GF enabled us to bring GNSS functionality from car navigation systems to smartphones, the new chip at 1mW will open the door for GNSS to get integrated into wearable devices. That market, loaded with applications such as lifelog or babysitting, is huge."

This story was originally published on EE Times. To read the rest of the article, please click here.