New CISC architecture takes on RISC

The real power of the CISC approach will be most apparent in small-footprint IoT designs.

A recent study in the ACM Transactions on Computer Systems came to the conclusion that processor instruction set architectures, whether reduced (RISC) or complex (CISC), are irrelevant to basic power and performance in today's designs, particularly in relation to either the Arm or Intel processors. However, there may be reasons to believe that a new CISC ISA, created for modern compilers without the limitations of compatibility with low level legacy code, could be more effective than either alternative.

Imsys has taken that leap of faith and is giving CISC another try. The company has begun extensive evaluation of a 3.5sqmm test chip with a dual-core, CISC-based processor architecture with on-chip main memory for software and data. It is fabricated in 65nm CMOS.

To make it easy for developers to evaluate and port existing code, the processor incorporates a CISC ISA optimized for use with compilers based on LLVM for C/C++ (and other languages). The chip's ISA currently has about 1,100 opcodes, with instruction sizes in the 1 to 10-byte range, with an average of 3.15 bytes. According to Stefan Blixt, chief technical officer at Imsys, the new instruction set is close to the LLVM intermediate representation, i.e., the starting point for the compiler backend, which results in more efficient translation and higher code density than when targeting legacy CISC or RISC instruction sets.

To read the full article, please go to EETimes.

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