Process makes smaller, cheaper chips

Global SourcesUpdated on 2023/12/01

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Berkeley shows implant replacing SADP to produce chips as small as 9nm.

The TII approach created features as small as 9nm. Images: Peng Zheng via EE Times

Berkeley researchers described a technique that they say cuts the cost and time of making leading-edge chips while creating features smaller than today's most advanced processes. The so-called tilted ion implantation or TII process created features as small as 9 nm.

The lab work shows promise for reducing the rapidly increasing cost and complexity of making chips, which has slowed progress in Moore's law. However, it's unclear whether chipmakers will adopt the technique.

"We are using argon ions to selectively damage certain parts of the silicon dioxide layer," said Peng Zheng, lead author of a paper published in the latest issue of the IEEE Transactions on Electron Devices. "It's self-aligned, tilting down with pre-existing mask features, so it doesn't have the issues of [the existing] LELE [method], where misalignment is a killer."

The approach could cut 50 percent off the costs of the widely used self-align double patterning or SADP technique used today at 16nm and beyond while improving throughput by as much as 35 percent, he said.

To read the full article, go to EETimes.

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Process makes smaller, cheaper chips

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