The US$150,000 grand prize went to Indiana Integrated Circuits for its quilt packaging technique, which can provide optical waveguides connections between chips virtually free of charge.
Quilt packaging (QP) attaches die together using hexagonal (or square) form factors that snap together to create interconnected systems that can mix processes, such as CMOS, GaAs, and MEMS, on the same quilt. (Source: Indiana Integrated Circuits, EE Times)
The Elevator Pitch Session, a contest recently sponsored by MEMS Industry Group (MIG) brought out dozens of submissions competing for a US$150,000 purse. Narrowed down to six entrants, finalists were allowed to give a five-minute pitch with five slides, and another five minutes for questions in front of a live audience.
The $150,000 iGrant, which went to Indiana Integrated Circuits (IIC) for its quilt packaging technique, was provided by Rogue Valley Microdevices and the Sustainable Valley Technology Group.
IIC won the Elevator Pitch Session this year with its unique "quilt packaging" technique for 2-D or 3-D chips. Quilt packaging (QP) attaches die together using hexagonal (or square) form factors that snap together to create fully interconnected systems that are "More than Moore," according to its president, Jason Kulick. Chosen by a panel of investment experts, IIC received US$150,000 iGrant to develop their concept plus a free year-long membership in the MEMS Industry Group.
"As CMOS size scaling has begun to reach the physical limits to how much transistor size can shrink, the semiconductor industry has recognized a need for more approaches than just traditional Moore's Law scaling in order to keep increasing performance/cost benefits on a 'Moore's Law-like' pace," Kulick told EE Times. "'More than Moore' is a collection of alternatives to the traditional approach. We think QP [quilted packaging] can be a similarly disruptive alternative to traditional packaging approaches."
The reason IIC won is because it integrates any number of chips -- MEMS sensors, sensor hubs, application processors -- without a printed circuit board (PCB). 2-D Quilt packaging allows the devices to be packed side-by-side with their interconnecting edges providing interfaces so fast and close as if they were integrated together on a system-on-chip (SoC). The advantage over SoCs is that quilt packaging can intermix different technologies, since they do not share a common substrate -- such as GaAs, Silicon and MEMS on the same quilt -- as well as provide optical waveguides connections between chips virtually free of charge.
"Once the individual quilt packaged chips are reflowed together into a 'quilt,' the quilt is then treated as if it were a large chip. It can be bumped,wirebonded, flipped, mounted to ceramic, PCB, or put in a traditional package," Kulick told us.